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yosys/techlibs/ice40
History
Stefan Riesenberger baa3659ea5 ice40: Fix path delay definitions 
Parallel connections do not allow matching different bit widths.
A full connection has to be used instead.
Allows iverilog to parse the simulation library with hardware path delays enabled.
2023-03-10 10:48:05 +01:00
..
tests
abc9_model.v Fix icestorm links 2021-06-09 12:39:12 +02:00
arith_map.v
brams.txt ice40: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_map.v ice40: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
cells_map.v
cells_sim.v ice40: Fix path delay definitions 2023-03-10 10:48:05 +01:00
dsp_map.v
ff_map.v
ice40_braminit.cc
ice40_opt.cc
latches_map.v
Makefile.inc ice40: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
spram.txt ice40: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
spram_map.v ice40: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
synth_ice40.cc Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00