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74 lines
1.8 KiB
Text
74 lines
1.8 KiB
Text
read_verilog -icells <<EOT
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module sr(input R, S, output [2:0] Q);
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$_SR_PP_ ff0 (.R(R), .S(S), .Q(Q[0]));
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$_SR_PN_ ff1 (.R(R), .S(S), .Q(Q[1]));
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$_SR_NP_ ff2 (.R(R), .S(S), .Q(Q[2]));
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endmodule
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EOT
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design -save orig
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equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ x
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equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
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equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ x
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equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
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equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
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equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
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# Convert everything to SRs.
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design -load orig
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dfflegalize -cell $_SR_PP_ x
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select -assert-count 2 t:$_NOT_
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select -assert-count 3 t:$_SR_PP_
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select -assert-none t:$_SR_PP_ t:$_NOT_ %% %n t:* %i
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# Convert everything to ADLATCHs.
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design -load orig
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dfflegalize -cell $_DLATCH_PP0_ x
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select -assert-count 2 t:$_NOT_
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select -assert-count 3 t:$_DLATCH_PP0_
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select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i
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design -load orig
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dfflegalize -cell $_DLATCH_PP1_ x
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select -assert-count 8 t:$_NOT_
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select -assert-count 3 t:$_DLATCH_PP1_
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select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ %% %n t:* %i
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# Convert everything to DLATCHSRs.
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design -load orig
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dfflegalize -cell $_DLATCHSR_PPP_ x
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select -assert-count 2 t:$_NOT_
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select -assert-count 3 t:$_DLATCHSR_PPP_
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select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i
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# Convert everything to DFFSRs.
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design -load orig
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dfflegalize -cell $_DFFSR_PPP_ x
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select -assert-count 2 t:$_NOT_
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select -assert-count 3 t:$_DFFSR_PPP_
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select -assert-none t:$_DFFSR_PPP_ t:$_NOT_ %% %n t:* %i
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# Convert everything to DFFSREs.
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design -load orig
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dfflegalize -cell $_DFFSRE_PPPP_ x
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select -assert-count 2 t:$_NOT_
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select -assert-count 3 t:$_DFFSRE_PPPP_
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select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ %% %n t:* %i
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