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62 lines
1.7 KiB
Verilog
62 lines
1.7 KiB
Verilog
module partsel_test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down);
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wire [5:0] offset = idx << 2;
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assign slice_up = data[offset +: 4];
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assign slice_down = data[offset + 3 -: 4];
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endmodule
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module partsel_test002 (
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input clk, rst,
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input [7:0] a,
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input [0:7] b,
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input [1:0] s,
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output [7:0] x1, x2, x3,
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output [0:7] x4, x5, x6,
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output [7:0] y1, y2, y3,
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output [0:7] y4, y5, y6,
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output [7:0] z1, z2, z3,
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output [0:7] z4, z5, z6,
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output [7:0] w1, w2, w3,
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output [0:7] w4, w5, w6,
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output [7:0] p1, p2, p3, p4, p5, p6,
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output [0:7] q1, q2, q3, q4, q5, q6,
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output reg [7:0] r1,
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output reg [0:7] r2
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);
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assign x1 = a, x2 = a + b, x3 = b;
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assign x4 = a, x5 = a + b, x6 = b;
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assign y1 = a[4 +: 3], y2 = a[4 +: 3] + b[4 +: 3], y3 = b[4 +: 3];
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assign y4 = a[4 +: 3], y5 = a[4 +: 3] + b[4 +: 3], y6 = b[4 +: 3];
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assign z1 = a[4 -: 3], z2 = a[4 -: 3] + b[4 -: 3], z3 = b[4 -: 3];
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assign z4 = a[4 -: 3], z5 = a[4 -: 3] + b[4 -: 3], z6 = b[4 -: 3];
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assign w1 = a[6:3], w2 = a[6:3] + b[3:6], w3 = b[3:6];
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assign w4 = a[6:3], w5 = a[6:3] + b[3:6], w6 = b[3:6];
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assign p1 = a[s], p2 = b[s], p3 = a[s+2 +: 2], p4 = b[s+2 +: 2], p5 = a[s+2 -: 2], p6 = b[s+2 -: 2];
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assign q1 = a[s], q2 = b[s], q3 = a[s+2 +: 2], q4 = b[s+2 +: 2], q5 = a[s+2 -: 2], q6 = b[s+2 -: 2];
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always @(posedge clk) begin
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if (rst) begin
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{ r1, r2 } = 16'h1337 ^ {a, b};
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end else begin
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case (s)
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0: begin
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r1[3:0] <= r2[0:3] ^ x1;
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r2[4:7] <= r1[7:4] ^ x4;
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end
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1: begin
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r1[2 +: 3] <= r2[5 -: 3] + x1;
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r2[3 +: 3] <= r1[6 -: 3] + x4;
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end
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2: begin
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r1[6 -: 3] <= r2[3 +: 3] - x1;
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r2[7 -: 3] <= r1[4 +: 3] - x4;
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end
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3: begin
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r1 <= r2;
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r2 <= r1;
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end
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endcase
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end
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end
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endmodule
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