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yosys/backends
whitequark da65e1e8d9 write_verilog: correctly emit asynchronous transparent ports.
This commit fixes two related issues:
  * For asynchronous ports, clock is no longer added to domain list.
    (This would lead to absurd constructs like `always @(posedge 0)`.
  * The logic to distinguish synchronous and asynchronous ports is
    changed to correctly use or avoid clock in all cases.

Before this commit, the following RTLIL snippet (after memory_collect)

    cell $memrd $2
      parameter \MEMID "\\mem"
      parameter \ABITS 2
      parameter \WIDTH 4
      parameter \CLK_ENABLE 0
      parameter \CLK_POLARITY 1
      parameter \TRANSPARENT 1
      connect \CLK 1'0
      connect \EN 1'1
      connect \ADDR \mem_r_addr
      connect \DATA \mem_r_data
    end

would lead to invalid Verilog:

    reg [1:0] _0_;
    always @(posedge 1'h0) begin
      _0_ <= mem_r_addr;
    end
    assign mem_r_data = mem[_0_];

Note that there are two potential pitfalls remaining after this
change:
  * For asynchronous ports, the \EN input and \TRANSPARENT parameter
    are silently ignored. (Per discussion in #760 this is the correct
    behavior.)
  * For synchronous transparent ports, the \EN input is ignored. This
    matches the behavior of the $mem simulation cell. Again, see #760.
2019-01-29 02:24:00 +00:00
..
aiger Add "write_aiger -I -O -B" 2018-11-12 09:27:33 +01:00
blif Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
btor Minor style fixes 2018-12-18 20:02:39 +01:00
edif Add "write_edif -gndvccy" 2019-01-17 13:33:11 +01:00
firrtl added prefix to FDirection constants, fixing windows build 2018-09-21 20:43:49 +02:00
ilang Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
intersynth Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
json Merge pull request #591 from hzeller/virtual-override 2018-08-15 14:05:38 +02:00
protobuf Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
simplec Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
smt2 Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
smv Minor update 2018-10-15 13:54:12 -04:00
spice Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
table Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
verilog write_verilog: correctly emit asynchronous transparent ports. 2019-01-29 02:24:00 +00:00