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https://github.com/YosysHQ/yosys
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42 lines
1.2 KiB
C++
42 lines
1.2 KiB
C++
#include "kernel/rtlil.h"
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#include "kernel/yosys.h"
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#include "kernel/unstable/patch.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct TestPatchPass : public Pass {
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TestPatchPass() : Pass("test_patch", "test patcher") { }
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void help() override
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{
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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(void) args;
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design->sigNormalize();
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for (auto module : design->selected_modules()) {
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SigMap sigmap(module);
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for (auto cell : module->selected_cells()) {
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if (cell->type == TW($add)) {
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Cell* add = cell;
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log_assert(add->getPort(TW::B).is_wire());
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log_assert(add->getPort(TW::B).known_driver());
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auto neg = add->getPort(TW::B)[0].wire->driverCell();
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log_assert(neg->type == TW($not));
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RTLIL::Patch patcher(module, nullptr);
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int width = cell->getPort(TW::A).size();
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auto sub = patcher.addSub(NEW_TWINE,
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neg->getPort(TW::A),
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add->getPort(TW::A),
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patcher.addWire(NEW_TWINE, width));
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auto new_out_wire = patcher.addWire(NEW_TWINE, width);
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auto new_cell = patcher.addNeg(NEW_TWINE, sub->getPort(TW::Y), new_out_wire);
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log_cell(new_cell);
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patcher.patch(add, TW::Y, new_out_wire);
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}
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}
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}
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}
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} TestPatchPass;
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PRIVATE_NAMESPACE_END
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