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25680f6a07
Adds test case that fails without code change. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
22 lines
355 B
Verilog
22 lines
355 B
Verilog
module top(
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input clk,
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input rst,
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input [2:0] a,
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output [1:0] b
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);
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reg [2:0] b_reg;
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initial begin
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b_reg <= 3'b0;
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end
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assign b = b_reg[1:0];
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always @(posedge clk or posedge rst) begin
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if(rst) begin
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b_reg <= 3'b0;
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end else begin
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b_reg <= a;
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end
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end
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endmodule
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