mirror of
https://github.com/YosysHQ/yosys
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106 lines
3.1 KiB
C++
106 lines
3.1 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2025 King Lok Chung <king.chung@manchester.ac.uk>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static std::string celltype, cell_portname, cell_paramname;
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static RTLIL::Module *module;
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static RTLIL::SigChunk value;
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void constmap_worker(RTLIL::SigSpec &sig)
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{
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if (sig.is_fully_const()){
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value = module->addWire(NEW_ID, sig.size());
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RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
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cell->setParam(cell_paramname, sig.as_const());
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cell->setPort(cell_portname, value);
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sig = value;
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}
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}
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struct ConstmapPass : public Pass {
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ConstmapPass() : Pass("constmap", "technology mapping of coarse constant value") { }
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void help() override
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{
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log("\n");
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log(" constmap [options] [selection]\n");
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log("\n");
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log("Map constants to a driver cell.\n");
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log("\n");
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log(" -cell <celltype> <portname> <paramname>\n");
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log(" Replace constant bits with this cell.\n");
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log(" The value of the constant will be stored to the parameter specified.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing CONSTMAP pass (mapping to constant driver).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-cell" && argidx+3 < args.size()){
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celltype = RTLIL::escape_id(args[++argidx]);
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cell_portname = RTLIL::escape_id(args[++argidx]);
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cell_paramname = RTLIL::escape_id(args[++argidx]);
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (design->has(celltype)) {
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Module *existing = design->module(celltype);
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bool has_port = false;
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for (auto &p : existing->ports){
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if (p == cell_portname){
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has_port = true;
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break;
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}
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}
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if (!has_port)
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log_cmd_error("Cell type '%s' does not have port '%s'.\n", celltype, cell_portname);
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bool has_param = false;
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for (auto &p : existing->avail_parameters){
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if (p == cell_paramname)
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has_param = true;
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}
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if (!has_param)
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log_cmd_error("Cell type '%s' does not have parameter '%s'.\n", celltype, cell_paramname);
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}
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for (auto mod : design->selected_modules())
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{
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module = mod;
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module->rewrite_sigspecs(constmap_worker);
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}
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}
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} ConstmapPass;
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PRIVATE_NAMESPACE_END
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