mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity
yosys/tests/arch
History
Lofty f4298b057a quicklogic: PolarPro 3 support 
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
2021-03-18 13:28:16 +01:00
..
anlogic tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
common intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00
ecp5 Blackbox all whiteboxes after synthesis 2021-03-17 21:07:20 +00:00
efinix tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
gowin tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
ice40 tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
intel_alm tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
machxo2 machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values. 2021-02-23 17:39:58 +01:00
nexus nexus: DSP inference support 2020-11-20 08:45:55 +00:00
quicklogic quicklogic: PolarPro 3 support 2021-03-18 13:28:16 +01:00
xilinx ast: Use better parameter serialization for paramod names. 2021-03-18 00:52:00 +01:00
run-test.sh tests: extend tests/arch/run-tests.sh for defines 2020-03-05 08:08:32 -08:00