mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
11 lines
149 B
Verilog
11 lines
149 B
Verilog
module test(input A, B, C, D, E,
|
|
output reg Y);
|
|
always @* begin
|
|
Y <= A;
|
|
if (B)
|
|
Y <= C;
|
|
if (D)
|
|
Y <= E;
|
|
end
|
|
endmodule
|