mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
7 lines
134 B
Verilog
7 lines
134 B
Verilog
module MYMUL(A, B, Y);
|
|
parameter WIDTH = 1;
|
|
input [WIDTH-1:0] A, B;
|
|
output [WIDTH-1:0] Y;
|
|
assign Y = A * B;
|
|
endmodule
|