mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
5 lines
83 B
Verilog
5 lines
83 B
Verilog
module test(A, B, Y);
|
|
input [1:0] A, B;
|
|
output [1:0] Y = A * B;
|
|
endmodule
|