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11 lines
130 B
Verilog
11 lines
130 B
Verilog
module DSP48_MACC (a, b, c, y);
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input [17:0] a;
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input [24:0] b;
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input [47:0] c;
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output [47:0] y;
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assign y = a*b + c;
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endmodule
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