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yosys/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
2014-02-21 02:13:02 +01:00

14 lines
303 B
Verilog

module test1(a, b, c, d, e, f, y);
input [19:0] a, b, c;
input [15:0] d, e, f;
output [41:0] y;
assign y = a*b + c*d + e*f;
endmodule
module test2(a, b, c, d, e, f, y);
input [19:0] a, b, c;
input [15:0] d, e, f;
output [41:0] y;
assign y = a*b + (c*d + e*f);
endmodule