mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
15 lines
195 B
Verilog
15 lines
195 B
Verilog
module uut_always02(clock,
|
|
reset, count);
|
|
|
|
input clock, reset;
|
|
output [3:0] count;
|
|
reg [3:0] count;
|
|
|
|
always @(posedge clock) begin
|
|
count <= count + 1;
|
|
if (reset)
|
|
count <= 0;
|
|
end
|
|
|
|
endmodule
|