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11 lines
212 B
Verilog
11 lines
212 B
Verilog
module splice_demo(a, b, c, d, e, f, x, y);
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input [1:0] a, b, c, d, e, f;
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output [1:0] x = {a[0], a[1]};
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output [11:0] y;
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assign {y[11:4], y[1:0], y[3:2]} =
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{a, b, -{c, d}, ~{e, f}};
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endmodule
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