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yosys/techlibs/common
Scott Ashcroft 04bbd4e7e2 Make all vector-size related integer params in $print sim model signed
This fixes iverilog crashes on 32-bit, similar to 95944eb for $mem.
2025-03-25 13:08:49 +00:00
..
choices
.gitignore
abc9_map.v
abc9_model.v
abc9_unmap.v
adff2dff.v
cellhelp.py
cells.lib
cmp2lcu.v
cmp2lut.v
cmp2softlogic.v
dff2ff.v
gate2lut.v
gen_fine_ffs.py
Makefile.inc
mul2dsp.v
pmux2mux.v
prep.cc
simcells.v
simlib.v
smtmap.v
synth.cc
techmap.v