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7 lines
175 B
Plaintext
7 lines
175 B
Plaintext
read_verilog mux.v
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synth_ice40
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equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40
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design -load postopt
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select -assert-count 20 t:SB_LUT4
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select -assert-count 1 t:SB_CARRY
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