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48 lines
980 B
Verilog
48 lines
980 B
Verilog
module assert_dff(input clk, input test, input pat);
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always @(posedge clk)
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begin
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#1;
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if (test != pat)
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begin
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$display("ERROR: ASSERTION FAILED in %m:",$time);
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$stop;
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end
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end
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endmodule
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module assert_tri(input en, input A, input B);
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always @(posedge en)
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begin
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#1;
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if (A !== B)
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begin
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$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
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$stop;
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end
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end
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endmodule
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module assert_Z(input clk, input A);
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always @(posedge clk)
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begin
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#1;
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if (A === 1'bZ)
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begin
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$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
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$stop;
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end
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end
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endmodule
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module assert_comb(input A, input B);
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always @(*)
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begin
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#1;
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if (A !== B)
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begin
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$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
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$stop;
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end
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end
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endmodule
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