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yosys/examples/cmos
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Larry Doolittle 2021ddecb3 Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
..
.gitignore Cleanups and improvements in examples/cmos/ 2016-03-11 11:30:01 +01:00
cmos_cells.lib
cmos_cells.sp
cmos_cells.v
cmos_cells_digital.sp
counter.v
counter.ys
counter_digital.ys Completed ngspice digital example with verilog tb 2016-03-05 08:34:05 +01:00
counter_tb.gtkw Cleanups and improvements in examples/cmos/ 2016-03-11 11:30:01 +01:00
counter_tb.v Squelch trailing whitespace 2017-04-12 15:11:09 +02:00
README Cleanups and improvements in examples/cmos/ 2016-03-11 11:30:01 +01:00
testbench.sh Cleanups and improvements in examples/cmos/ 2016-03-11 11:30:01 +01:00
testbench.sp
testbench_digital.sh Squelch trailing whitespace 2017-04-12 15:11:09 +02:00
testbench_digital.sp Completed ngspice digital example with verilog tb 2016-03-05 08:34:05 +01:00

README 

In this directory contains an example for generating a spice output using two
different spice modes, normal analog transient simulation and event-driven
digital simulation as supported by ngspice xspice sub-module.

Each test bench can be run separately by either running:

- testbench.sh, to start analog simulation or
- testbench_digital.sh for mixed-signal digital simulation.

The later case also includes pure verilog simulation using the iverilog
and gtkwave for comparison.