whitequark 4f426c2ac4 write_verilog: do not print (*init*) attributes on regs. ... If an init value is emitted for a reg, an (*init*) attribute is never necessary, since it is exactly equivalent. On the other hand, some tools that consume Verilog (ISE, Vivado, Quartus) complain about (*init*) attributes because their interpretation differs from Yosys. All (*init*) attributes that would not become reg init values anyway are emitted as before.		2019-09-22 16:52:06 +00:00
..
Makefile.inc	initial import	2013-01-05 11:13:26 +01:00
verilog_backend.cc	write_verilog: do not print (*init*) attributes on regs.	2019-09-22 16:52:06 +00:00