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yosys/frontends/verilog
Clifford Wolf d71529baa1
Merge pull request #562 from udif/pr_fix_illegal_port_decl
Detect illegal port declaration, e.g input/output/inout keyword must …
2018-08-15 13:14:23 +02:00
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.gitignore Updated .gitignore file for ilang and verilog frontends 2014-10-15 01:14:38 +02:00
const2ast.cc Convert more log_error() to log_file_error() where possible. 2018-07-20 09:37:44 -07:00
Makefile.inc Adjust makefiles to work with out-of-tree builds 2015-08-12 15:04:44 +02:00
preproc.cc Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
verilog_frontend.cc Use log_file_warning(), log_file_error() functions. 2018-07-20 08:19:06 -07:00
verilog_frontend.h Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
verilog_lexer.l Support more character literals 2018-05-03 12:35:01 +02:00
verilog_parser.y Detect illegal port declaration, e.g input/output/inout keyword must be the first. 2018-06-06 22:27:25 +03:00