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yosys/frontends/ast
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Clifford Wolf 3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error 
Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
2018-08-15 13:35:41 +02:00
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ast.cc Merge pull request #513 from udif/pr_reg_wire_error 2018-08-15 13:35:41 +02:00
ast.h Merge pull request #513 from udif/pr_reg_wire_error 2018-08-15 13:35:41 +02:00
dpicall.cc Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
genrtlil.cc Convert more log_error() to log_file_error() where possible. 2018-07-20 09:37:44 -07:00
Makefile.inc Added Verilog/AST support for DPI functions (dpi_call() still unimplemented) 2014-08-21 12:43:51 +02:00
simplify.cc Merge pull request #513 from udif/pr_reg_wire_error 2018-08-15 13:35:41 +02:00