|
example_basys3
|
Added Xilinx example for Basys3 board
|
2015-02-01 17:09:34 +01:00 |
|
tests
|
Improved xilinx "bram1" test
|
2015-04-09 17:12:12 +02:00 |
|
.gitignore
|
Added support for initialized xilinx brams
|
2015-04-06 17:07:10 +02:00 |
|
arith_map.v
|
Various cleanups in xilinx techlib
|
2015-01-18 19:43:54 +01:00 |
|
brams.txt
|
Added support for initialized xilinx brams
|
2015-04-06 17:07:10 +02:00 |
|
brams_bb.v
|
Added Xilinx bram black-box modules
|
2015-04-06 08:44:30 +02:00 |
|
brams_init.py
|
Added support for initialized xilinx brams
|
2015-04-06 17:07:10 +02:00 |
|
brams_map.v
|
Added support for initialized xilinx brams
|
2015-04-06 17:07:10 +02:00 |
|
cells_map.v
|
Various cleanups in xilinx techlib
|
2015-01-18 19:43:54 +01:00 |
|
cells_sim.v
|
Disabled (unused) Xilinx tristate buffers
|
2015-02-04 16:33:59 +01:00 |
|
drams.txt
|
Added memory_bram "make_outreg" feature
|
2015-04-09 16:08:54 +02:00 |
|
drams_bb.v
|
Xilinx DRAMS: RAM64X1D, RAM128X1D
|
2015-04-09 13:37:07 +02:00 |
|
drams_map.v
|
Xilinx DRAMS: RAM64X1D, RAM128X1D
|
2015-04-09 13:37:07 +02:00 |
|
Makefile.inc
|
Towards DRAM support in Xilinx flow
|
2015-04-09 08:17:14 +02:00 |
|
synth_xilinx.cc
|
Towards DRAM support in Xilinx flow
|
2015-04-09 08:17:14 +02:00 |
