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aiger
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Merge pull request #1359 from YosysHQ/xc7dsp
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2019-09-29 11:26:22 -07:00 |
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blif
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RTLIL::S{0,1} -> State::S{0,1}
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2019-08-07 11:12:38 -07:00 |
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btor
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Corrects btor2 backend
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2019-09-27 12:40:17 -04:00 |
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edif
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Add "whitebox" attribute, add "read_verilog -wb"
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2019-04-18 17:45:47 +02:00 |
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firrtl
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Merge pull request #1258 from YosysHQ/eddie/cleanup
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2019-08-10 09:52:14 +02:00 |
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ilang
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RTLIL::S{0,1} -> State::S{0,1}
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2019-08-07 11:12:38 -07:00 |
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intersynth
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substr() -> compare()
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2019-08-07 12:20:08 -07:00 |
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json
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Implement improved JSON attr/param encoding
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2019-08-01 12:34:52 +02:00 |
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protobuf
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Add aiger and protobuf backends binary support
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2019-09-28 09:51:48 +02:00 |
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smt2
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backends: smt2: use $(CXX) variable for compiler
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2019-09-08 15:47:09 +08:00 |
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smv
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substr() -> compare()
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2019-08-07 12:20:08 -07:00 |
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spice
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Add "whitebox" attribute, add "read_verilog -wb"
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2019-04-18 17:45:47 +02:00 |
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table
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Add "whitebox" attribute, add "read_verilog -wb"
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2019-04-18 17:45:47 +02:00 |
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verilog
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substr() -> compare()
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2019-08-07 12:20:08 -07:00 |
