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yosys/techlibs
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Tim 'mithro' Ansell d6bdefd2e9 Improving vpr output support. 
* Support output BLIF for Xilinx architectures.
 * Support using .names in BLIF for Xilinx architectures.
 * Use the same `NO_LUT` define in both `synth_ice40` and
  `synth_xilinx`.
2018-04-18 16:55:12 -07:00
..
achronix Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device 2018-03-31 22:48:47 -06:00
common Add "synth -noshare" 2018-03-04 17:13:45 +01:00
coolrunner2 coolrunner2: Add an ANDTERM/XOR between chained FFs 2018-03-31 03:54:48 -07:00
easic Add first draft of eASIC back-end 2017-09-29 17:53:43 +02:00
gowin Indenting fixes in gowin sim cell lib 2016-11-08 18:54:00 +01:00
greenpak4 Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted. 2017-09-14 10:26:32 -07:00
ice40 Improving vpr output support. 2018-04-18 16:55:12 -07:00
intel Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device 2018-03-31 22:48:47 -06:00
xilinx Improving vpr output support. 2018-04-18 16:55:12 -07:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00