3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-07 09:55:20 +00:00
yosys/tests
Kamil Rakoczy d69ddf19da Add typedef input/output test
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-01-18 17:31:22 +01:00
..
aiger switch argument order to work with macOS getopt 2020-09-23 12:48:26 +02:00
arch nexus: DSP inference support 2020-11-20 08:45:55 +00:00
asicworld
bram
errors
fsm tests: fsm to use a randomly-generated seed 2020-04-24 14:31:33 -07:00
hana
liberty dfflibmap: Refactor to use dfflegalize internally. 2020-07-09 18:51:03 +02:00
lut Forgot to commit 2019-07-16 12:44:26 -07:00
memfile Added 'set -e' into tests/memfile/run-test.sh 2020-02-06 10:45:40 -03:00
memories tests: Parallelize 2020-09-21 15:07:02 +02:00
opt opt_share: Fix X and CO signal width for shifted $alu in opt_share. 2021-01-14 14:54:08 +01:00
opt_share tests: Parallelize 2020-09-21 15:07:02 +02:00
proc proc_clean: fix order of switch insertion. 2019-08-19 16:44:23 +00:00
realmath
rpc rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors 2020-03-06 15:29:01 +01:00
sat Merge pull request #2378 from udif/pr_dollar_high_low 2020-10-01 18:17:36 +02:00
select Merge pull request #1949 from YosysHQ/eddie/select_blackbox 2020-04-22 15:35:05 -07:00
share
simple tests/simple: remove "nullglob" shopt 2020-09-21 15:07:02 +02:00
simple_abc9 abc9: test to use box file instead of auto 2020-05-14 10:33:56 -07:00
smv
sva
svinterfaces
svtypes Add typedef input/output test 2021-01-18 17:31:22 +01:00
techmap tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
tools Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
unit
various Merge pull request #2518 from zachjs/recursion 2021-01-01 09:32:26 +00:00
verilog Merge pull request #2380 from Xiretza/parallel-tests 2020-10-01 18:12:31 +02:00
vloghtb
gen-tests-makefile.sh tests: Parallelize 2020-09-21 15:07:02 +02:00