Jannis Harder 79e05a195d verilog: Bufnorm cell backend and frontend support ... This makes the Verilog backend handle the $connect and $input_port cells. This represents the undirected $connect cell using the `tran` primitive, so we also extend the frontend to support this.		2025-09-17 14:01:09 +02:00
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aiger
aiger2	write_aiger2: Ignore the $input_port cell during indexing.	2025-09-17 13:56:46 +02:00
blif
btor	Update backends to avoid bits()	2025-09-16 03:17:23 +00:00
cxxrtl	Remove .c_str() from log_cmd_error() and log_file_error() parameters	2025-09-16 22:59:08 +00:00
edif	Remove unnecessary .c_str() in EDIF_ macros	2025-09-16 23:14:11 +00:00
firrtl	Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix()	2025-09-16 23:02:16 +00:00
functional	Update backends to avoid bits()	2025-09-16 03:17:23 +00:00
intersynth
jny
json
rtlil
simplec	Update backends to avoid bits()	2025-09-16 03:17:23 +00:00
smt2	Update backends to avoid bits()	2025-09-16 03:17:23 +00:00
smv
spice
table
verilog	verilog: Bufnorm cell backend and frontend support	2025-09-17 14:01:09 +02:00