mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-30 19:22:31 +00:00
23 lines
832 B
Text
23 lines
832 B
Text
read_verilog ../common/dffs.v
|
|
design -save read
|
|
|
|
hierarchy -top dff
|
|
proc
|
|
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd dff # Constrain all select calls below inside the top module
|
|
select -assert-count 1 t:EFX_FF
|
|
select -assert-count 1 t:EFX_GBUFCE
|
|
|
|
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
|
|
|
|
design -load read
|
|
hierarchy -top dffe
|
|
proc
|
|
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd dffe # Constrain all select calls below inside the top module
|
|
select -assert-count 1 t:EFX_FF
|
|
select -assert-count 1 t:EFX_GBUFCE
|
|
|
|
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
|