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yosys/tests/verilog/parameters_across_files.ys
George Rennie dfa8453102 tests: remove -seq 1 from sat with -tempinduct where possible
* When used with -tempinduct mode, -seq <N> causes assertions to be
  ignored in the first N steps. While this has uses for reset modelling,
  for these test cases it is unnecessary and could lead to failures
  slipping through uncaught
2024-10-03 16:39:17 +02:00

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read_verilog -sv <<EOF
parameter Q = 1;
EOF
read_verilog -sv <<EOF
parameter P = Q;
module top(
output integer out
);
assign out = P;
always @*
assert (out == 1);
endmodule
EOF
hierarchy
proc
flatten
opt -full
async2sync
select -module top
sat -verify -tempinduct -prove-asserts -show-all