Eddie Hung de26328130 Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cell ... write_xaiger to treat unknown cell connections as keep-s		2019-07-03 09:43:00 -07:00
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aiger	tests: use optional ABCEXTERNAL when specified	2019-06-27 23:00:13 -04:00
arch	Add simcells.v, simlib.v, and some output	2019-06-27 11:13:49 -07:00
asicworld	Fix FIRRTL to Verilog process instance subfield assignment.	2019-02-25 16:18:13 -08:00
bram
errors	Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,	2018-10-25 02:37:56 +03:00
fsm
hana
liberty	Liberty file parser now accepts superfluous ;	2019-03-27 15:16:19 +01:00
lut	cmp2lut: new techmap pass.	2019-01-02 07:53:31 +00:00
memories	memory_dff: Fix checking of feedback mux input when more than one mux	2019-07-02 13:35:50 +01:00
opt	Refactor "opt_rmdff -sat"	2019-06-20 13:44:21 +02:00
realmath
sat	support repeat loops with constant repeat counts outside of constant functions	2019-04-09 12:28:32 -04:00
share
simple	Add test	2019-06-20 16:07:22 -07:00
simple_abc9	Fix issue with part of PI being 1'bx	2019-06-20 17:38:16 -07:00
smv
sva	Fix "verific -extnets" for more complex situations	2019-03-26 14:17:46 +01:00
svinterfaces	Fix typo in tests/svinterfaces/runone.sh	2019-05-03 14:40:51 +02:00
techmap	Move tests/techmap/abc9 to simple_abc9	2019-02-20 15:34:59 -08:00
tools	autotest.sh to define _AUTOTB when test_autotb	2019-06-28 14:56:22 -07:00
unit	Build hotfix in tests/unit/Makefile	2016-12-11 10:58:49 +01:00
various	Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cell	2019-07-03 09:43:00 -07:00
vloghtb	bugfix in blif front-end	2015-05-18 11:15:49 +02:00