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69 lines
1.8 KiB
Text
69 lines
1.8 KiB
Text
read_verilog init.v
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read_verilog -lib -specify +/gowin/cells_sim.v
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design -save read
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proc
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flatten
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synth_gowin -run coarse:
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# check if all init values are handled
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check -assert -noinit
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# check if every flop mapped correctly
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select -assert-count 1 t:DFF
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select -assert-count 1 t:DFFC
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select -assert-count 1 t:DFFCE
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select -assert-count 1 t:DFFE
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select -assert-count 1 t:DFFN
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select -assert-count 1 t:DFFNC
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select -assert-count 1 t:DFFNCE
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select -assert-count 1 t:DFFNE
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select -assert-count 1 t:DFFNP
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select -assert-count 1 t:DFFNPE
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select -assert-count 1 t:DFFNR
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select -assert-count 1 t:DFFNRE
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select -assert-count 1 t:DFFNS
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select -assert-count 1 t:DFFNSE
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select -assert-count 1 t:DFFP
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select -assert-count 1 t:DFFPE
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select -assert-count 1 t:DFFR
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select -assert-count 1 t:DFFRE
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select -assert-count 1 t:DFFS
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select -assert-count 1 t:DFFSE
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design -load read
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# these should synth to a flop with reset
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chparam -set INIT 1 myDFF myDFFN myDFFE myDFFNE
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# async would give an error
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# sync should synth to a mux
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chparam -set INIT 0 myDFF*S*
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chparam -set INIT 1 myDFF*R*
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proc
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flatten
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synth_gowin -run coarse:
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# check the flops mapped as expected
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select -assert-count 2 t:DFF
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select -assert-count 1 t:DFFC
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select -assert-count 1 t:DFFCE
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select -assert-count 0 t:DFFE
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select -assert-count 2 t:DFFN
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select -assert-count 1 t:DFFNC
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select -assert-count 1 t:DFFNCE
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select -assert-count 0 t:DFFNE
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select -assert-count 1 t:DFFNP
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select -assert-count 1 t:DFFNPE
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select -assert-count 0 t:DFFNR
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select -assert-count 0 t:DFFNRE
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select -assert-count 3 t:DFFNS
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select -assert-count 1 t:DFFNSE
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select -assert-count 1 t:DFFP
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select -assert-count 1 t:DFFPE
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select -assert-count 0 t:DFFR
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select -assert-count 0 t:DFFRE
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select -assert-count 3 t:DFFS
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select -assert-count 1 t:DFFSE
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select -assert-count 4 t:LUT2
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select -assert-count 4 t:LUT4
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