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Code
Activity
d320e75087
yosys
/
passes
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Clifford Wolf
d320e75087
document "techmap -map %<design-name>"
2014-08-15 02:01:30 +02:00
..
abc
Added module->ports
2014-08-14 16:22:52 +02:00
cmds
RIP $safe_pmux
2014-08-14 11:39:46 +02:00
fsm
RIP $safe_pmux
2014-08-14 11:39:46 +02:00
hierarchy
Added module->ports
2014-08-14 16:22:52 +02:00
memory
Various improvements in memory_dff pass
2014-08-06 14:31:38 +02:00
opt
RIP $safe_pmux
2014-08-14 11:39:46 +02:00
proc
Fixed handling of constant-true branches in proc_clean
2014-08-12 17:35:22 +02:00
sat
Fixed "share" for complex scenarios with never-active cells
2014-08-09 17:07:20 +02:00
techmap
document "techmap -map %<design-name>"
2014-08-15 02:01:30 +02:00
tests
RIP $safe_pmux
2014-08-14 11:39:46 +02:00