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yosys/techlibs/gowin
History
YRabbit d60dc93e92 Gowin. Renaming inputs of the DCS primitive. 
The dynamic clock selection (DCS) primitive has undergone changes with
the release of the GW5A series—the CLK0,1,2,3 inputs are now
CLKIN0,1,2,3, but only for GW5A series chips.

There are no functional changes, only renaming.

Here we are transferring the description of the DCS primitive from
general to specialized files for each chip series.

We have also fixed a bug in the generation script that caused the loss
of primitive parameters. Fortunately, this only affected the
analog-to-digital converter, which has not yet been implemented.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-09-20 16:22:23 +01:00
..
arith_map.v gowin: Fix X output of $alu techmap 2023-05-01 17:56:41 +02:00
brams.txt gowin: Change BYTE ENABLE handling. 2024-01-27 17:19:49 +10:00
brams_map.v gowin: Fix SDP write enable port. 2024-01-30 17:06:59 +10:00
cells_map.v iopadmap: Add native support for negative-polarity output enable. 2021-11-09 15:40:16 +01:00
cells_sim.v Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
cells_xtra.py Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
cells_xtra_gw1n.v Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
cells_xtra_gw2a.v Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
cells_xtra_gw5a.v Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
lutrams.txt gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
lutrams_map.v gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Makefile.inc gowin: split cells_xtra by family 2024-11-26 15:42:22 +01:00
synth_gowin.cc Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00