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23 lines
266 B
Text
23 lines
266 B
Text
read_verilog << EOT
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module top(...);
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input D1, D2, R, CLK;
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output reg Q1, Q2;
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always @(posedge CLK, posedge R) begin
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Q1 <= 0;
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if (!R) begin
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Q1 <= D1;
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Q2 <= D2;
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end
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end
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endmodule
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EOT
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proc
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opt
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select -assert-count 1 t:$adff
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select -assert-count 1 t:$dffe
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