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d30f934d0d
Based on existing code for input cone and the `sat` handling of `-set-assumes`. Update `equiv_assume.ys` to use `-set-assumes` option.
28 lines
539 B
Text
28 lines
539 B
Text
read_verilog -sv <<EOT
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module gold (input D, output Q);
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assign Q = '0;
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endmodule
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module gate (input D, output Q);
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assume property (D == '0);
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assign Q = D;
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endmodule
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EOT
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chformal -lower
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async2sync
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design -stash input
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# using $assert cells in sat verifies
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design -load input
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equiv_make -make_assert gold gate equiv
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prep -top equiv
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sat -set-assumes -prove-asserts -verify
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# this fails
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# sat -prove-asserts -verify
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# so should $equiv
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design -load input
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equiv_make gold gate equiv
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equiv_simple -set-assumes equiv
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equiv_status -assert equiv
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