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13 lines
188 B
Text
13 lines
188 B
Text
read_verilog <<EOT
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module simple(I1, I2, O);
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input wire I1;
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input wire I2;
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output wire O;
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assign O = I1 | I2;
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endmodule
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EOT
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techmap
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logger -warn " /tmp/" -werror " /tmp/"
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abc -g all
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