mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-13 20:38:44 +00:00
38a0c30d65
This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
702 lines
24 KiB
C++
702 lines
24 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* (C) 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SynthXilinxPass : public ScriptPass
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{
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SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
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void on_register() YS_OVERRIDE
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{
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RTLIL::constpad["synth_xilinx.abc9.xc7.W"] = "300"; // Number with which ABC will map a 6-input gate
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// to one LUT6 (instead of a LUT5 + LUT2)
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}
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_xilinx [options]\n");
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log("\n");
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log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
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log("partly selected designs. At the moment this command creates netlists that are\n");
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log("compatible with 7-Series Xilinx devices.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module\n");
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log("\n");
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log(" -family <family>\n");
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log(" run synthesis for the specified Xilinx architecture\n");
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log(" generate the synthesis netlist for the specified family.\n");
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log(" supported values:\n");
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log(" - xcup: Ultrascale Plus\n");
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log(" - xcu: Ultrascale\n");
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log(" - xc7: Series 7 (default)\n");
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log(" - xc6s: Spartan 6\n");
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log(" - xc6v: Virtex 6\n");
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log(" - xc5v: Virtex 5 (EXPERIMENTAL)\n");
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log(" - xc4v: Virtex 4 (EXPERIMENTAL)\n");
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log(" - xc3sda: Spartan 3A DSP (EXPERIMENTAL)\n");
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log(" - xc3sa: Spartan 3A (EXPERIMENTAL)\n");
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log(" - xc3se: Spartan 3E (EXPERIMENTAL)\n");
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log(" - xc3s: Spartan 3 (EXPERIMENTAL)\n");
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log(" - xc2vp: Virtex 2 Pro (EXPERIMENTAL)\n");
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log(" - xc2v: Virtex 2 (EXPERIMENTAL)\n");
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log(" - xcve: Virtex E, Spartan 2E (EXPERIMENTAL)\n");
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log(" - xcv: Virtex, Spartan 2 (EXPERIMENTAL)\n");
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log("\n");
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log(" -edif <file>\n");
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log(" write the design to the specified edif file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -blif <file>\n");
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log(" write the design to the specified BLIF file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -vpr\n");
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log(" generate an output netlist (and BLIF file) suitable for VPR\n");
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log(" (this feature is experimental and incomplete)\n");
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log("\n");
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log(" -ise\n");
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log(" generate an output netlist suitable for ISE\n");
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log("\n");
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log(" -nobram\n");
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log(" do not use block RAM cells in output netlist\n");
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log("\n");
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log(" -nolutram\n");
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log(" do not use distributed RAM cells in output netlist\n");
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log("\n");
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log(" -nosrl\n");
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log(" do not use distributed SRL cells in output netlist\n");
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log("\n");
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log(" -nocarry\n");
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log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
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log("\n");
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log(" -nowidelut\n");
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log(" do not use MUXF[5-9] resources to implement LUTs larger than native for the target\n");
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log("\n");
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log(" -nodsp\n");
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log(" do not use DSP48*s to implement multipliers and associated logic\n");
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log("\n");
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log(" -noiopad\n");
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log(" disable I/O buffer insertion (useful for hierarchical or \n");
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log(" out-of-context flows)\n");
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log("\n");
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log(" -noclkbuf\n");
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log(" disable automatic clock buffer insertion\n");
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log("\n");
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log(" -uram\n");
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log(" infer URAM288s for large memories (xcup only)\n");
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log("\n");
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log(" -widemux <int>\n");
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log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
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log(" above this number of inputs (minimum value 2, recommended value >= 5).\n");
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log(" default: 0 (no inference)\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -flatten\n");
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log(" flatten design before synthesis\n");
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log("\n");
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log(" -dff\n");
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log(" run 'abc'/'abc9' with -dff option\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with '-D 1' option to enable flip-flop retiming.\n");
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log(" implies -dff.\n");
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log("\n");
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log(" -abc9\n");
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log(" use new ABC9 flow (EXPERIMENTAL)\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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std::string top_opt, edif_file, blif_file, family;
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bool flatten, retime, vpr, ise, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram;
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bool abc9, dff_mode;
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bool flatten_before_abc;
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int widemux;
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int lut_size;
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int widelut_size;
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void clear_flags() YS_OVERRIDE
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{
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top_opt = "-auto-top";
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edif_file.clear();
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blif_file.clear();
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family = "xc7";
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flatten = false;
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retime = false;
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vpr = false;
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ise = false;
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noiopad = false;
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noclkbuf = false;
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nocarry = false;
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nobram = false;
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nolutram = false;
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nosrl = false;
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nocarry = false;
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nowidelut = false;
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nodsp = false;
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uram = false;
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abc9 = false;
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dff_mode = false;
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flatten_before_abc = false;
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widemux = 0;
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lut_size = 6;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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std::string run_from, run_to;
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
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family = args[++argidx];
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continue;
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}
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if (args[argidx] == "-edif" && argidx+1 < args.size()) {
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edif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-blif" && argidx+1 < args.size()) {
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blif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-flatten") {
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flatten = true;
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continue;
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}
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if (args[argidx] == "-flatten_before_abc") {
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flatten_before_abc = true;
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continue;
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}
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if (args[argidx] == "-retime") {
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dff_mode = true;
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retime = true;
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continue;
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}
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if (args[argidx] == "-nocarry") {
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nocarry = true;
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continue;
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}
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if (args[argidx] == "-nowidelut") {
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nowidelut = true;
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continue;
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}
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if (args[argidx] == "-vpr") {
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vpr = true;
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continue;
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}
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if (args[argidx] == "-ise") {
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ise = true;
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continue;
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}
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if (args[argidx] == "-iopad") {
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continue;
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}
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if (args[argidx] == "-noiopad") {
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noiopad = true;
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continue;
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}
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if (args[argidx] == "-noclkbuf") {
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noclkbuf = true;
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continue;
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}
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if (args[argidx] == "-nocarry") {
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nocarry = true;
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continue;
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}
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if (args[argidx] == "-nobram") {
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nobram = true;
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continue;
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}
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if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
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nolutram = true;
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continue;
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}
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if (args[argidx] == "-nosrl") {
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nosrl = true;
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continue;
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}
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if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
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widemux = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-abc9") {
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abc9 = true;
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continue;
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}
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if (args[argidx] == "-nodsp") {
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nodsp = true;
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continue;
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}
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if (args[argidx] == "-uram") {
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uram = true;
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continue;
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}
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if (args[argidx] == "-dff") {
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dff_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (family == "xcup" || family == "xcu") {
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lut_size = 6;
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widelut_size = 9;
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} else if (family == "xc7" ||
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family == "xc6v" ||
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family == "xc5v" ||
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family == "xc6s") {
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lut_size = 6;
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widelut_size = 8;
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} else if (family == "xc4v" ||
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family == "xc3sda" ||
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family == "xc3sa" ||
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family == "xc3se" ||
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family == "xc3s" ||
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family == "xc2vp" ||
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family == "xc2v") {
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lut_size = 4;
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widelut_size = 8;
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} else if (family == "xcve" || family == "xcv") {
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lut_size = 4;
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widelut_size = 6;
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} else
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log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
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if (widemux != 0 && lut_size != 6)
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log_cmd_error("-widemux is not currently supported for LUT4-based architectures.\n");
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if (lut_size != 6) {
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log_warning("Shift register inference not yet supported for family %s.\n", family.c_str());
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nosrl = true;
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}
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if (widemux != 0 && widemux < 2)
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log_cmd_error("-widemux value must be 0 or >= 2.\n");
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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if (abc9 && retime)
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log_cmd_error("-retime option not currently compatible with -abc9!\n");
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log_header(design, "Executing SYNTH_XILINX pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() YS_OVERRIDE
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{
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std::string lut_size_s = std::to_string(lut_size);
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if (help_mode)
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lut_size_s = "[46]";
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std::string ff_map_file;
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if (help_mode)
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ff_map_file = "+/xilinx/{family}_ff_map.v";
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else if (family == "xc6s")
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ff_map_file = "+/xilinx/xc6s_ff_map.v";
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else
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ff_map_file = "+/xilinx/xc7_ff_map.v";
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if (check_label("begin")) {
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std::string read_args;
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if (vpr)
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read_args += " -D_EXPLICIT_CARRY";
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read_args += " -lib -specify +/xilinx/cells_sim.v";
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run("read_verilog" + read_args);
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run("read_verilog -lib +/xilinx/cells_xtra.v");
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run(stringf("hierarchy -check %s", top_opt.c_str()));
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}
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if (check_label("prepare")) {
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run("proc");
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if (flatten || help_mode)
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run("flatten", "(with '-flatten')");
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if (active_design)
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active_design->scratchpad_unset("tribuf.added_something");
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run("tribuf -logic");
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if (noiopad && active_design && active_design->scratchpad_get_bool("tribuf.added_something"))
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log_error("Tristate buffers are unsupported without the '-iopad' option.\n");
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run("deminout");
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run("opt_expr");
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run("opt_clean");
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run("check");
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run("opt");
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if (help_mode)
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run("wreduce [-keepdc]", "(option for '-widemux')");
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else
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run("wreduce" + std::string(widemux > 0 ? " -keepdc" : ""));
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run("peepopt");
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run("opt_clean");
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if (widemux > 0 || help_mode)
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run("muxpack", " ('-widemux' only)");
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// xilinx_srl looks for $shiftx cells for identifying variable-length
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// shift registers, so attempt to convert $pmux-es to this
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// Also: wide multiplexer inference benefits from this too
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if (!(nosrl && widemux == 0) || help_mode) {
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run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
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run("clean", " (skip if '-nosrl' and '-widemux=0')");
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}
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}
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if (check_label("map_dsp", "(skip if '-nodsp')")) {
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if (!nodsp || help_mode) {
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run("memory_dff"); // xilinx_dsp will merge registers, reserve memory port registers first
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// NB: Xilinx multipliers are signed only
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if (help_mode)
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run("techmap -map +/mul2dsp.v -map +/xilinx/{family}_dsp_map.v {options}");
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else if (family == "xc2v" || family == "xc2vp" || family == "xc3s" || family == "xc3se" || family == "xc3sa")
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run("techmap -map +/mul2dsp.v -map +/xilinx/xc3s_mult_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
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"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
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"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
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"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
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else if (family == "xc3sda")
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run("techmap -map +/mul2dsp.v -map +/xilinx/xc3sda_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
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"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
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"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
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"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
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else if (family == "xc6s")
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run("techmap -map +/mul2dsp.v -map +/xilinx/xc6s_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
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"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
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"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
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"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
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else if (family == "xc4v")
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run("techmap -map +/mul2dsp.v -map +/xilinx/xc4v_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
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"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
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"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
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"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
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else if (family == "xc5v")
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run("techmap -map +/mul2dsp.v -map +/xilinx/xc5v_dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 "
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"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
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"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
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"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
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else if (family == "xc6v" || family == "xc7")
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run("techmap -map +/mul2dsp.v -map +/xilinx/xc7_dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 "
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"-D DSP_A_MAXWIDTH_PARTIAL=18 " // Partial multipliers are intentionally
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// limited to 18x18 in order to take
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// advantage of the (PCOUT << 17) -> PCIN
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// dedicated cascade chain capability
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"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
|
|
"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
|
|
"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
|
|
else if (family == "xcu" || family == "xcup")
|
|
run("techmap -map +/mul2dsp.v -map +/xilinx/xcu_dsp_map.v -D DSP_A_MAXWIDTH=27 -D DSP_B_MAXWIDTH=18 "
|
|
"-D DSP_A_MAXWIDTH_PARTIAL=18 " // Partial multipliers are intentionally
|
|
// limited to 18x18 in order to take
|
|
// advantage of the (PCOUT << 17) -> PCIN
|
|
// dedicated cascade chain capability
|
|
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
|
|
"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
|
|
"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL27X18");
|
|
run("select a:mul2dsp");
|
|
run("setattr -unset mul2dsp");
|
|
run("opt_expr -fine");
|
|
run("wreduce");
|
|
run("select -clear");
|
|
if (help_mode)
|
|
run("xilinx_dsp -family <family>");
|
|
else
|
|
run("xilinx_dsp -family " + family);
|
|
run("chtype -set $mul t:$__soft_mul");
|
|
}
|
|
}
|
|
|
|
if (check_label("coarse")) {
|
|
run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=" + lut_size_s);
|
|
run("alumacc");
|
|
run("share");
|
|
run("opt");
|
|
run("fsm");
|
|
run("opt -fast");
|
|
run("memory -nomap");
|
|
run("opt_clean");
|
|
}
|
|
|
|
if (check_label("map_uram", "(only if '-uram')")) {
|
|
if (help_mode) {
|
|
run("memory_bram -rules +/xilinx/{family}_urams.txt");
|
|
run("techmap -map +/xilinx/{family}_urams_map.v");
|
|
} else if (uram) {
|
|
if (family == "xcup") {
|
|
run("memory_bram -rules +/xilinx/xcup_urams.txt");
|
|
run("techmap -map +/xilinx/xcup_urams_map.v");
|
|
} else {
|
|
log_warning("UltraRAM inference not supported for family %s.\n", family.c_str());
|
|
}
|
|
}
|
|
}
|
|
|
|
if (check_label("map_bram", "(skip if '-nobram')")) {
|
|
if (help_mode) {
|
|
run("memory_bram -rules +/xilinx/{family}_brams.txt");
|
|
run("techmap -map +/xilinx/{family}_brams_map.v");
|
|
} else if (!nobram) {
|
|
if (family == "xc2v" || family == "xc2vp" || family == "xc3s" || family == "xc3se") {
|
|
run("memory_bram -rules +/xilinx/xc2v_brams.txt");
|
|
run("techmap -map +/xilinx/xc2v_brams_map.v");
|
|
} else if (family == "xc3sa") {
|
|
// Superset of Virtex 2 primitives — uses common map file.
|
|
run("memory_bram -rules +/xilinx/xc3sa_brams.txt");
|
|
run("techmap -map +/xilinx/xc2v_brams_map.v");
|
|
} else if (family == "xc3sda") {
|
|
// Supported block RAMs for Spartan 3A DSP are
|
|
// a subset of Spartan 6's ones.
|
|
run("memory_bram -rules +/xilinx/xc3sda_brams.txt");
|
|
run("techmap -map +/xilinx/xc6s_brams_map.v");
|
|
} else if (family == "xc6s") {
|
|
run("memory_bram -rules +/xilinx/xc6s_brams.txt");
|
|
run("techmap -map +/xilinx/xc6s_brams_map.v");
|
|
} else if (family == "xc6v" || family == "xc7") {
|
|
run("memory_bram -rules +/xilinx/xc7_xcu_brams.txt");
|
|
run("techmap -map +/xilinx/xc7_brams_map.v");
|
|
} else if (family == "xcu" || family == "xcup") {
|
|
run("memory_bram -rules +/xilinx/xc7_xcu_brams.txt");
|
|
run("techmap -map +/xilinx/xcu_brams_map.v");
|
|
} else {
|
|
log_warning("Block RAM inference not yet supported for family %s.\n", family.c_str());
|
|
}
|
|
}
|
|
}
|
|
|
|
if (check_label("map_lutram", "(skip if '-nolutram')")) {
|
|
if (!nolutram || help_mode) {
|
|
run("memory_bram -rules +/xilinx/lut" + lut_size_s + "_lutrams.txt");
|
|
run("techmap -map +/xilinx/lutrams_map.v");
|
|
}
|
|
}
|
|
|
|
if (check_label("map_ffram")) {
|
|
// Required for dff2dffs to work.
|
|
run("simplemap t:$dff t:$adff t:$mux");
|
|
// Needs to be done before opt -mux_bool happens.
|
|
if (help_mode)
|
|
run("dff2dffs [-match-init]", "(-match-init for xc6s only)");
|
|
else if (family == "xc6s")
|
|
run("dff2dffs -match-init");
|
|
else
|
|
run("dff2dffs");
|
|
if (widemux > 0)
|
|
run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover
|
|
// performs less efficiently
|
|
else
|
|
run("opt -fast -full");
|
|
run("memory_map");
|
|
}
|
|
|
|
if (check_label("fine")) {
|
|
run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
|
|
if (help_mode)
|
|
run("muxcover <internal options> ('-widemux' only)");
|
|
else if (widemux > 0) {
|
|
constexpr int cost_mux2 = 100;
|
|
std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2);
|
|
switch (widemux) {
|
|
case 2: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2+1, cost_mux2+2, cost_mux2+3); break;
|
|
case 3:
|
|
case 4: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-2, cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
|
|
case 5:
|
|
case 6:
|
|
case 7:
|
|
case 8: muxcover_args += stringf(" -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
|
|
case 9:
|
|
case 10:
|
|
case 11:
|
|
case 12:
|
|
case 13:
|
|
case 14:
|
|
case 15:
|
|
default: muxcover_args += stringf(" -mux16=%d", cost_mux2*(widemux-1)-1); break;
|
|
}
|
|
run("muxcover " + muxcover_args);
|
|
}
|
|
run("opt -full");
|
|
|
|
if (!nosrl || help_mode)
|
|
run("xilinx_srl -variable -minlen 3", "(skip if '-nosrl')");
|
|
|
|
std::string techmap_args = " -map +/techmap.v -D LUT_SIZE=" + lut_size_s;
|
|
if (help_mode)
|
|
techmap_args += " [-map +/xilinx/mux_map.v]";
|
|
else if (widemux > 0)
|
|
techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", widemux);
|
|
if (!nocarry) {
|
|
techmap_args += " -map +/xilinx/arith_map.v";
|
|
if (vpr)
|
|
techmap_args += " -D _EXPLICIT_CARRY";
|
|
}
|
|
run("techmap " + techmap_args);
|
|
run("opt -fast");
|
|
}
|
|
|
|
if (check_label("map_cells")) {
|
|
// Needs to be done before logic optimization, so that inverters (OE vs T) are handled.
|
|
if (help_mode || !noiopad)
|
|
run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad $__XILINX_TOUTPAD OE:I:O -tinoutpad $__XILINX_TINOUTPAD OE:O:I:IO A:top", "(skip if '-noiopad')");
|
|
std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
|
|
if (widemux > 0)
|
|
techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
|
|
run("techmap " + techmap_args);
|
|
run("clean");
|
|
}
|
|
|
|
if (check_label("map_ffs")) {
|
|
if (abc9 || help_mode) {
|
|
run("techmap -map " + ff_map_file, "('-abc9' only)");
|
|
}
|
|
}
|
|
|
|
if (check_label("map_luts")) {
|
|
run("opt_expr -mux_undef");
|
|
if (flatten_before_abc)
|
|
run("flatten");
|
|
if (help_mode)
|
|
run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for 'nowidelut', '-dff', '-retime')");
|
|
else if (abc9) {
|
|
if (lut_size != 6)
|
|
log_error("'synth_xilinx -abc9' not currently supported for LUT4-based devices.\n");
|
|
if (family != "xc7")
|
|
log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
|
|
"will use timing for 'xc7' instead.\n", family.c_str());
|
|
std::string techmap_args = "-map +/xilinx/abc9_map.v -max_iter 1";
|
|
if (dff_mode)
|
|
techmap_args += " -D DFF_MODE";
|
|
run("techmap " + techmap_args);
|
|
run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v");
|
|
std::string abc9_opts;
|
|
auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
|
|
if (active_design->scratchpad.count(k))
|
|
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
|
|
else
|
|
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str());
|
|
if (nowidelut)
|
|
abc9_opts += stringf(" -maxlut %d", lut_size);
|
|
if (dff_mode)
|
|
abc9_opts += " -dff";
|
|
run("abc9" + abc9_opts);
|
|
run("techmap -map +/xilinx/abc9_unmap.v");
|
|
}
|
|
else {
|
|
std::string abc_opts;
|
|
if (lut_size != 6) {
|
|
if (nowidelut)
|
|
abc_opts += " -lut " + lut_size_s;
|
|
else
|
|
abc_opts += " -lut " + lut_size_s + ":" + std::to_string(widelut_size);
|
|
} else {
|
|
if (nowidelut)
|
|
abc_opts += " -luts 2:2,3,6:5";
|
|
else if (widelut_size == 8)
|
|
abc_opts += " -luts 2:2,3,6:5,10,20";
|
|
else
|
|
abc_opts += " -luts 2:2,3,6:5,10,20,40";
|
|
}
|
|
if (dff_mode)
|
|
abc_opts += " -dff";
|
|
if (retime)
|
|
abc_opts += " -D 1";
|
|
run("abc" + abc_opts);
|
|
}
|
|
run("clean");
|
|
|
|
// This shregmap call infers fixed length shift registers after abc
|
|
// has performed any necessary retiming
|
|
if (!nosrl || help_mode)
|
|
run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
|
|
std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
|
|
if (help_mode || !abc9)
|
|
techmap_args += stringf(" -map %s", ff_map_file.c_str());
|
|
techmap_args += " -D LUT_WIDTH=" + lut_size_s;
|
|
run("techmap " + techmap_args);
|
|
if (help_mode)
|
|
run("xilinx_dffopt [-lut4]");
|
|
else if (lut_size == 4)
|
|
run("xilinx_dffopt -lut4");
|
|
else
|
|
run("xilinx_dffopt");
|
|
run("opt_lut_ins -tech xilinx");
|
|
}
|
|
|
|
if (check_label("finalize")) {
|
|
if (help_mode || !noclkbuf)
|
|
run("clkbufmap -buf BUFG O:I", "(skip if '-noclkbuf')");
|
|
if (help_mode || ise)
|
|
run("extractinv -inv INV O:I", "(only if '-ise')");
|
|
run("clean");
|
|
}
|
|
|
|
if (check_label("check")) {
|
|
run("hierarchy -check");
|
|
run("stat -tech xilinx");
|
|
run("check -noinit");
|
|
}
|
|
|
|
if (check_label("edif")) {
|
|
if (!edif_file.empty() || help_mode)
|
|
run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
|
|
}
|
|
|
|
if (check_label("blif")) {
|
|
if (!blif_file.empty() || help_mode)
|
|
run(stringf("write_blif %s", edif_file.c_str()));
|
|
}
|
|
}
|
|
} SynthXilinxPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|