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19 lines
456 B
Text
19 lines
456 B
Text
read_verilog <<EOF
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module gate(input signed [2:0] a1, input signed [2:0] b1,
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input [1:0] a2, input [3:0] b2, input c, input d, output signed [3:0] y);
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wire signed [3:0] ab1;
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assign ab1 = a1 * b1;
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assign y = ab1 + a2*b2 + c + d + 1;
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endmodule
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EOF
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prep
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design -save gold
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alumacc
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opt_clean
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select -assert-count 1 t:$macc_v2
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maccmap -unmap
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design -copy-from gold -as gold gate
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equiv_make gold gate equiv
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equiv_induct equiv
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equiv_status -assert equiv
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