mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity
yosys/techlibs/quicklogic
History
Emil J. Tywoniak d2b28d7a25 s/NEW_ID/NEWER_ID/g
2025-09-16 17:43:02 +02:00
..
common synth_quicklogic: rearrange files to prepare for adding more architectures 2023-12-04 15:52:02 +01:00
pp3 synth_quicklogic: rearrange files to prepare for adding more architectures 2023-12-04 15:52:02 +01:00
qlf_k6n10f Drop timestamp in generate_bram_types_sim.py 2024-10-30 08:47:18 +01:00
.gitignore add dsp inference 2023-12-04 15:52:02 +01:00
Makefile.inc add ioff inference for qlf_k6n10f 2025-01-24 21:17:15 +01:00
ql_bram_merge.cc s/NEW_ID/NEWER_ID/g 2025-09-16 17:43:02 +02:00
ql_bram_types.cc add dsp inference 2023-12-04 15:52:02 +01:00
ql_dsp_io_regs.cc Fix Windows build by forcing initialization order, fixes #4068 2024-01-02 11:26:48 +01:00
ql_dsp_macc.cc s/NEW_ID/NEWER_ID/g 2025-09-16 17:43:02 +02:00
ql_dsp_macc.pmg ql_dsp_macc: Tune DSP inference code 2023-12-04 15:52:02 +01:00
ql_dsp_simd.cc s/NEW_ID/NEWER_ID/g 2025-09-16 17:43:02 +02:00
ql_ioff.cc s/NEW_ID/NEWER_ID/g 2025-09-16 17:43:02 +02:00
synth_quicklogic.cc Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00