Eddie Hung 562c9e3624 Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules		2019-08-16 15:40:53 -07:00
..
tests	Improved xilinx "bram1" test	2015-04-09 17:12:12 +02:00
.gitignore
abc_xc7.box	Fix $__XILINX_MUXF78 box timing	2019-07-01 14:04:06 -07:00
abc_xc7.lut
abc_xc7_nowide.lut	Add _nowide variants of LUT libraries in -nowidelut flows	2019-06-26 10:23:29 -07:00
arith_map.v
brams_init.py	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
cells_map.v	xilinx: Fix missing cell name underscore in cells_map.v	2019-07-25 08:19:07 +01:00
cells_sim.v	Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules	2019-08-16 15:40:53 -07:00
cells_xtra.sh
cells_xtra.v
drams.txt
drams_map.v
ff_map.v	xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.	2019-07-11 21:13:12 +02:00
lut_map.v
Makefile.inc	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
mux_map.v
synth_xilinx.cc	stoi -> atoi	2019-08-07 11:09:17 -07:00
xc6s_brams.txt	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
xc6s_brams_bb.v	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
xc6s_brams_map.v	RST -> RSTBRST for RAMB8BWER	2019-07-29 16:05:44 -07:00
xc7_brams.txt	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
xc7_brams_bb.v	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
xc7_brams_map.v	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00