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yosys/techlibs/xilinx
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Clifford Wolf bfcd46dbd3
Merge pull request #842 from litghost/merge_upstream 
Changes required for VPR place and route in synth_xilinx
2019-03-05 15:33:19 -08:00
..
tests
.gitignore
arith_map.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
brams.txt
brams_bb.v
brams_init.py Squelch trailing whitespace, including meta-whitespace 2018-03-11 16:03:41 +01:00
brams_map.v Revert BRAM WRITE_MODE changes. 2019-03-04 09:22:22 -08:00
cells_map.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
cells_sim.v Revert FF models to include IS_x_INVERTED parameters. 2019-03-01 14:41:21 -08:00
cells_xtra.sh Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
cells_xtra.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
drams.txt
drams_map.v
ff_map.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
lut_map.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
Makefile.inc Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
synth_xilinx.cc Merge pull request #842 from litghost/merge_upstream 2019-03-05 15:33:19 -08:00