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https://github.com/YosysHQ/yosys
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79 lines
1.6 KiB
Verilog
79 lines
1.6 KiB
Verilog
module \$__NX_MUL36X36 (input [35:0] A, input [35:0] B, output [71:0] Y);
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parameter A_WIDTH = 36;
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parameter B_WIDTH = 36;
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parameter Y_WIDTH = 72;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT36X36 #(
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.REGINPUTA("BYPASS"),
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.REGINPUTB("BYPASS"),
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.REGOUTPUT("BYPASS")
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) _TECHMAP_REPLACE_ (
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.A(A), .B(B),
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.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),
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.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),
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.Z(Y)
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);
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endmodule
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module \$__NX_MUL36X18 (input [35:0] A, input [17:0] B, output [53:0] Y);
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parameter A_WIDTH = 36;
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parameter B_WIDTH = 18;
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parameter Y_WIDTH = 54;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT18X36 #(
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.REGINPUTA("BYPASS"),
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.REGINPUTB("BYPASS"),
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.REGOUTPUT("BYPASS")
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) _TECHMAP_REPLACE_ (
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.A(B), .B(A),
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.SIGNEDA(B_SIGNED ? 1'b1 : 1'b0),
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.SIGNEDB(A_SIGNED ? 1'b1 : 1'b0),
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.Z(Y)
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);
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endmodule
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module \$__NX_MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
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parameter A_WIDTH = 18;
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parameter B_WIDTH = 18;
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parameter Y_WIDTH = 36;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT18X18 #(
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.REGINPUTA("BYPASS"),
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.REGINPUTB("BYPASS"),
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.REGOUTPUT("BYPASS")
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) _TECHMAP_REPLACE_ (
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.A(A), .B(B),
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.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),
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.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),
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.Z(Y)
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);
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endmodule
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module \$__NX_MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);
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parameter A_WIDTH = 9;
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parameter B_WIDTH = 9;
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parameter Y_WIDTH = 18;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT9X9 #(
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.REGINPUTA("BYPASS"),
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.REGINPUTB("BYPASS"),
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.REGOUTPUT("BYPASS")
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) _TECHMAP_REPLACE_ (
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.A(A), .B(B),
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.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),
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.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),
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.Z(Y)
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);
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endmodule
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