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yosys/frontends/verilog
2020-02-21 09:15:17 -08:00
..
.gitignore
const2ast.cc
Makefile.inc
preproc.cc Fixed some missing "verilog_" in documentation 2019-12-13 10:17:05 -03:00
verilog_frontend.cc Add "verilog_defines -list" and "verilog_defines -reset" 2019-10-21 13:35:56 +02:00
verilog_frontend.h
verilog_lexer.l verilog: ignore '&&&' when not in -specify mode 2020-02-13 13:06:13 -08:00
verilog_parser.y Merge pull request #1703 from YosysHQ/eddie/specify_improve 2020-02-21 09:15:17 -08:00