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https://github.com/YosysHQ/yosys
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290 lines
6.7 KiB
Verilog
290 lines
6.7 KiB
Verilog
module $__XILINX_URAM_ (...);
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parameter OPTION_BYTEWIDTH = 8;
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localparam WR_BE_WIDTH = 72 / OPTION_BYTEWIDTH;
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parameter CLK_C_POL = 1;
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parameter PORT_A_CLK_POL = 1;
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parameter PORT_A_OPTION_RST_MODE = "SYNC";
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parameter PORT_B_CLK_POL = 1;
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parameter PORT_B_OPTION_RST_MODE = "SYNC";
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input CLK_C;
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input PORT_A_RD_SRST;
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input PORT_A_RD_ARST;
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input PORT_A_WR_EN;
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input [WR_BE_WIDTH-1:0] PORT_A_WR_BE;
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input [11:0] PORT_A_ADDR;
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input [71:0] PORT_A_WR_DATA;
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output [71:0] PORT_A_RD_DATA;
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input PORT_B_CLK;
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input PORT_B_CLK_EN;
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input PORT_B_RD_SRST;
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input PORT_B_RD_ARST;
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input PORT_B_WR_EN;
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input [WR_BE_WIDTH-1:0] PORT_B_WR_BE;
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input [11:0] PORT_B_ADDR;
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input [71:0] PORT_B_WR_DATA;
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output [71:0] PORT_B_RD_DATA;
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wire [71:0] DIN_A, DIN_B, DOUT_A, DOUT_B;
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generate
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if (OPTION_BYTEWIDTH == 8) begin
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assign DIN_A = PORT_A_WR_DATA;
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assign DIN_B = PORT_B_WR_DATA;
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assign PORT_A_RD_DATA = DOUT_A;
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assign PORT_B_RD_DATA = DOUT_B;
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end else begin
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assign DIN_A = {
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PORT_A_WR_DATA[71],
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PORT_A_WR_DATA[62],
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PORT_A_WR_DATA[53],
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PORT_A_WR_DATA[44],
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PORT_A_WR_DATA[35],
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PORT_A_WR_DATA[26],
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PORT_A_WR_DATA[17],
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PORT_A_WR_DATA[8],
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PORT_A_WR_DATA[70:63],
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PORT_A_WR_DATA[61:54],
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PORT_A_WR_DATA[52:45],
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PORT_A_WR_DATA[43:36],
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PORT_A_WR_DATA[34:27],
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PORT_A_WR_DATA[25:18],
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PORT_A_WR_DATA[16:9],
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PORT_A_WR_DATA[7:0]
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};
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assign DIN_B = {
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PORT_B_WR_DATA[71],
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PORT_B_WR_DATA[62],
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PORT_B_WR_DATA[53],
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PORT_B_WR_DATA[44],
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PORT_B_WR_DATA[35],
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PORT_B_WR_DATA[26],
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PORT_B_WR_DATA[17],
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PORT_B_WR_DATA[8],
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PORT_B_WR_DATA[70:63],
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PORT_B_WR_DATA[61:54],
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PORT_B_WR_DATA[52:45],
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PORT_B_WR_DATA[43:36],
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PORT_B_WR_DATA[34:27],
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PORT_B_WR_DATA[25:18],
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PORT_B_WR_DATA[16:9],
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PORT_B_WR_DATA[7:0]
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};
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assign PORT_A_RD_DATA = {
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DOUT_A[71],
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DOUT_A[63:56],
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DOUT_A[70],
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DOUT_A[55:48],
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DOUT_A[69],
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DOUT_A[47:40],
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DOUT_A[68],
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DOUT_A[39:32],
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DOUT_A[67],
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DOUT_A[31:24],
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DOUT_A[66],
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DOUT_A[23:16],
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DOUT_A[65],
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DOUT_A[15:8],
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DOUT_A[64],
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DOUT_A[7:0]
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};
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assign PORT_B_RD_DATA = {
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DOUT_B[71],
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DOUT_B[63:56],
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DOUT_B[70],
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DOUT_B[55:48],
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DOUT_B[69],
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DOUT_B[47:40],
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DOUT_B[68],
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DOUT_B[39:32],
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DOUT_B[67],
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DOUT_B[31:24],
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DOUT_B[66],
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DOUT_B[23:16],
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DOUT_B[65],
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DOUT_B[15:8],
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DOUT_B[64],
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DOUT_B[7:0]
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};
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end
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endgenerate
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URAM288 #(
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.BWE_MODE_A(OPTION_BYTEWIDTH == 8 ? "PARITY_INDEPENDENT" : "PARITY_INTERLEAVED"),
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.BWE_MODE_B(OPTION_BYTEWIDTH == 8 ? "PARITY_INDEPENDENT" : "PARITY_INTERLEAVED"),
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.EN_AUTO_SLEEP_MODE("FALSE"),
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.IREG_PRE_A("FALSE"),
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.IREG_PRE_B("FALSE"),
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.IS_CLK_INVERTED(!CLK_C_POL),
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.OREG_A("FALSE"),
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.OREG_B("FALSE"),
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.RST_MODE_A(PORT_A_OPTION_RST_MODE),
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.RST_MODE_B(PORT_B_OPTION_RST_MODE),
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) _TECHMAP_REPLACE_ (
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.ADDR_A({11'b0, PORT_A_ADDR}),
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.BWE_A(PORT_A_WR_BE),
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.EN_A(PORT_A_CLK_EN),
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.RDB_WR_A(PORT_A_WR_EN),
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.INJECT_DBITERR_A(1'b0),
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.INJECT_SBITERR_A(1'b0),
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.RST_A(PORT_A_OPTION_RST_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST),
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.DIN_A(DIN_A),
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.DOUT_A(DOUT_A),
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.ADDR_B({11'b0, PORT_B_ADDR}),
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.BWE_B(PORT_B_WR_BE),
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.EN_B(PORT_B_CLK_EN),
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.RDB_WR_B(PORT_B_WR_EN),
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.INJECT_DBITERR_B(1'b0),
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.INJECT_SBITERR_B(1'b0),
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.RST_B(PORT_B_OPTION_RST_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST),
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.DIN_B(DIN_B),
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.DOUT_B(DOUT_B),
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.CLK(CLK_C),
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.SLEEP(1'b0)
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);
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endmodule
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module $__XILINX_URAM_SP_ (...);
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parameter OPTION_BYTEWIDTH = 8;
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localparam WR_BE_WIDTH = 144 / OPTION_BYTEWIDTH;
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parameter CLK_C_POL = 1;
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parameter PORT_A_CLK_POL = 1;
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parameter PORT_A_OPTION_RST_MODE = "SYNC";
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input CLK_C;
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input PORT_A_RD_SRST;
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input PORT_A_RD_ARST;
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input PORT_A_WR_EN;
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input [WR_BE_WIDTH-1:0] PORT_A_WR_BE;
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input [10:0] PORT_A_ADDR;
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input [143:0] PORT_A_WR_DATA;
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output [143:0] PORT_A_RD_DATA;
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wire [71:0] DIN_A, DIN_B, DOUT_A, DOUT_B;
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generate
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if (OPTION_BYTEWIDTH == 8) begin
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assign DIN_A = PORT_A_WR_DATA[71:0];
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assign DIN_B = PORT_A_WR_DATA[143:72];
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assign PORT_A_RD_DATA = {DOUT_B, DOUT_A};
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end else begin
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assign DIN_A = {
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PORT_A_WR_DATA[71],
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PORT_A_WR_DATA[62],
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PORT_A_WR_DATA[53],
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PORT_A_WR_DATA[44],
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PORT_A_WR_DATA[35],
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PORT_A_WR_DATA[26],
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PORT_A_WR_DATA[17],
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PORT_A_WR_DATA[8],
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PORT_A_WR_DATA[70:63],
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PORT_A_WR_DATA[61:54],
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PORT_A_WR_DATA[52:45],
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PORT_A_WR_DATA[43:36],
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PORT_A_WR_DATA[34:27],
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PORT_A_WR_DATA[25:18],
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PORT_A_WR_DATA[16:9],
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PORT_A_WR_DATA[7:0]
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};
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assign DIN_B = {
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PORT_A_WR_DATA[72+71],
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PORT_A_WR_DATA[72+62],
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PORT_A_WR_DATA[72+53],
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PORT_A_WR_DATA[72+44],
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PORT_A_WR_DATA[72+35],
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PORT_A_WR_DATA[72+26],
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PORT_A_WR_DATA[72+17],
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PORT_A_WR_DATA[72+8],
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PORT_A_WR_DATA[72+70:72+63],
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PORT_A_WR_DATA[72+61:72+54],
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PORT_A_WR_DATA[72+52:72+45],
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PORT_A_WR_DATA[72+43:72+36],
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PORT_A_WR_DATA[72+34:72+27],
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PORT_A_WR_DATA[72+25:72+18],
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PORT_A_WR_DATA[72+16:72+ 9],
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PORT_A_WR_DATA[72+ 7:72+ 0]
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};
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assign PORT_A_RD_DATA = {
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DOUT_B[71],
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DOUT_B[63:56],
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DOUT_B[70],
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DOUT_B[55:48],
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DOUT_B[69],
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DOUT_B[47:40],
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DOUT_B[68],
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DOUT_B[39:32],
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DOUT_B[67],
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DOUT_B[31:24],
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DOUT_B[66],
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DOUT_B[23:16],
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DOUT_B[65],
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DOUT_B[15:8],
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DOUT_B[64],
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DOUT_B[7:0],
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DOUT_A[71],
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DOUT_A[63:56],
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DOUT_A[70],
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DOUT_A[55:48],
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DOUT_A[69],
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DOUT_A[47:40],
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DOUT_A[68],
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DOUT_A[39:32],
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DOUT_A[67],
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DOUT_A[31:24],
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DOUT_A[66],
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DOUT_A[23:16],
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DOUT_A[65],
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DOUT_A[15:8],
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DOUT_A[64],
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DOUT_A[7:0]
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};
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end
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endgenerate
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URAM288 #(
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.BWE_MODE_A(OPTION_BYTEWIDTH == 8 ? "PARITY_INDEPENDENT" : "PARITY_INTERLEAVED"),
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.BWE_MODE_B(OPTION_BYTEWIDTH == 8 ? "PARITY_INDEPENDENT" : "PARITY_INTERLEAVED"),
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.EN_AUTO_SLEEP_MODE("FALSE"),
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.IREG_PRE_A("FALSE"),
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.IREG_PRE_B("FALSE"),
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.IS_CLK_INVERTED(!CLK_C_POL),
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.OREG_A("FALSE"),
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.OREG_B("FALSE"),
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.RST_MODE_A(PORT_A_OPTION_RST_MODE),
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.RST_MODE_B(PORT_A_OPTION_RST_MODE),
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) _TECHMAP_REPLACE_ (
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.ADDR_A({11'b0, PORT_A_ADDR, 1'b0}),
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.BWE_A(PORT_A_WR_BE[WR_BE_WIDTH/2-1:0]),
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.EN_A(PORT_A_CLK_EN),
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.RDB_WR_A(PORT_A_WR_EN),
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.INJECT_DBITERR_A(1'b0),
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.INJECT_SBITERR_A(1'b0),
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.RST_A(PORT_A_OPTION_RST_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST),
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.DIN_A(DIN_A),
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.DOUT_A(DOUT_A),
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.ADDR_B({11'b0, PORT_A_ADDR, 1'b1}),
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.BWE_B(PORT_A_WR_BE[WR_BE_WIDTH-1:WR_BE_WIDTH/2]),
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.EN_B(PORT_A_CLK_EN),
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.RDB_WR_B(PORT_A_WR_EN),
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.INJECT_DBITERR_B(1'b0),
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.INJECT_SBITERR_B(1'b0),
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.RST_B(PORT_A_OPTION_RST_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST),
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.DIN_B(DIN_B),
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.DOUT_B(DOUT_B),
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.CLK(CLK_C),
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.SLEEP(1'b0)
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);
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endmodule
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