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Code Activity
yosys/techlibs/xilinx
History
Clifford Wolf f42218682d Added examples/ top-level directory
2015-10-13 15:41:20 +02:00
..
tests Improved xilinx "bram1" test 2015-04-09 17:12:12 +02:00
.gitignore
arith_map.v Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
brams.txt Added read-enable to memory model 2015-09-25 12:23:11 +02:00
brams_bb.v
brams_init.py Switched to Python 3 2015-08-22 09:59:33 +02:00
brams_map.v Added read-enable to memory model 2015-09-25 12:23:11 +02:00
cells_map.v
cells_sim.v
drams.txt Added memory_bram "make_outreg" feature 2015-04-09 16:08:54 +02:00
drams_bb.v Xilinx DRAMS: RAM64X1D, RAM128X1D 2015-04-09 13:37:07 +02:00
drams_map.v Xilinx DRAMS: RAM64X1D, RAM128X1D 2015-04-09 13:37:07 +02:00
Makefile.inc Switched to Python 3 2015-08-22 09:59:33 +02:00
synth_xilinx.cc Added read-enable to memory model 2015-09-25 12:23:11 +02:00