Emil J. Tywoniak d13dfc21f4 WIP		2026-06-10 14:54:48 +02:00
..
cmds	WIP	2026-06-10 14:54:48 +02:00
equiv	WIP	2026-06-10 14:54:48 +02:00
fsm	WIP	2026-06-10 14:54:48 +02:00
hierarchy	rtlil: set Module::design before name at all construction sites	2026-06-10 14:54:39 +02:00
memory	WIP	2026-06-10 14:54:48 +02:00
opt	twine	2026-06-10 14:53:45 +02:00
pmgen	pmgen: hold sigmap pointer instead of owning it	2026-05-22 18:40:01 +02:00
proc	rtlil: set Module* on inner-process AttrObjects at construction	2026-06-10 14:54:12 +02:00
sat	WIP	2026-06-10 14:54:48 +02:00
techmap	WIP	2026-06-10 14:54:48 +02:00
tests	Refactored uses of log_id()	2026-05-08 20:59:24 -07:00