mirror of
https://github.com/YosysHQ/yosys
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72787f52fc
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
121 lines
4.8 KiB
Verilog
121 lines
4.8 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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`ifndef _NO_FFS
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// Async reset, enable.
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module \$_DFFE_NP0P_ (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFFE_NP1P_ (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFFE_PP1P_ (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// Async set and reset, enable.
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module \$_DFFSRE_NPPP_ (input D, C, E, S, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R), .PRE(S));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFFSRE_PPPP_ (input D, C, E, S, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R), .PRE(S));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// Sync reset, enable.
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module \$_SDFFE_NP0P_ (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_SDFFE_PP0P_ (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_SDFFE_NP1P_ (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_SDFFE_PP1P_ (input D, C, E, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// Latches with reset.
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module \$_DLATCH_NP0_ (input E, R, D, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DLATCH_PP0_ (input E, R, D, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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LDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DLATCH_NP1_ (input E, R, D, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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LDPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DLATCH_PP1_ (input E, R, D, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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LDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(R));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// Latches with set and reset.
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module \$_DLATCH_NPP_ (input E, S, R, D, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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LDCPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R), .PRE(S));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DLATCH_PPP_ (input E, S, R, D, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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LDCPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(R), .PRE(S));
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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`endif
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