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https://github.com/YosysHQ/yosys
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34 lines
855 B
Systemverilog
34 lines
855 B
Systemverilog
function [15:0] parse_init;
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input [((2+(16/4))*8)-1:0] init;
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reg [7:0] c;
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integer i;
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begin
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for (i = 0; i < (16/4); i = i + 1) begin
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c = init[(i * 8) +: 8];
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if (c >= "0" && c <= "9")
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parse_init[(i * 4) +: 4] = (c - "0");
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else if (c >= "A" && c <= "F")
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parse_init[(i * 4) +: 4] = (c - "A") + 10;
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else if (c >= "a" && c <= "f")
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parse_init[(i * 4) +: 4] = (c - "a") + 10;
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end
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end
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endfunction
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function [63:0] parse_init_64;
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input [((2+(64/4))*8)-1:0] init;
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reg [7:0] c;
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integer i;
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begin
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for (i = 0; i < (64/4); i = i + 1) begin
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c = init[(i * 8) +: 8];
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if (c >= "0" && c <= "9")
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parse_init_64[(i * 4) +: 4] = (c - "0");
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else if (c >= "A" && c <= "F")
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parse_init_64[(i * 4) +: 4] = (c - "A") + 10;
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else if (c >= "a" && c <= "f")
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parse_init_64[(i * 4) +: 4] = (c - "a") + 10;
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end
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end
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endfunction
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