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yosys/passes
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Marcin Kościelnicki fd0e3a2c43 Fix _TECHMAP_REMOVEINIT_ handling. 
Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.

Fixes the problem identified in #1396.
2019-09-27 18:34:12 +02:00
..
cmds Improve "portlist" command 2019-09-25 09:20:38 +02:00
equiv Add equiv_opt -multiclock 2019-09-11 13:55:59 +01:00
fsm RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
hierarchy Adopt @cliffordwolf's suggestion 2019-09-03 12:18:50 -07:00
memory stoi -> atoi 2019-08-07 11:09:17 -07:00
opt Revert "SigSet<Cell*> to use stable compare class" 2019-09-13 09:49:15 -07:00
pmgen Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext 2019-09-18 12:40:08 -07:00
proc proc_clean: fix order of switch insertion. 2019-08-19 16:44:23 +00:00
sat Revert "SigSet<Cell*> to use stable compare class" 2019-09-13 09:49:15 -07:00
techmap Fix _TECHMAP_REMOVEINIT_ handling. 2019-09-27 18:34:12 +02:00
tests Document (* gentb_skip *) attr for test_autotb 2019-09-18 12:41:35 -07:00