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yosys/techlibs/ice40
2019-07-13 01:11:00 -07:00
..
tests Bugfix in ice40_dsp 2019-02-21 13:28:46 +01:00
.gitignore
abc_hx.box Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box 2019-07-12 00:50:42 -07:00
abc_hx.lut Fix rename 2019-04-18 09:04:34 -07:00
abc_lp.box Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box 2019-07-12 00:50:42 -07:00
abc_lp.lut Rename to abc_*.{box,lut} 2019-04-18 09:02:58 -07:00
abc_u.box Off by one 2019-07-12 01:17:53 -07:00
abc_u.lut Rename to abc_*.{box,lut} 2019-04-18 09:02:58 -07:00
arith_map.v Fix spacing 2019-07-12 01:15:22 -07:00
brams.txt
brams_init.py
brams_map.v ice40: use 2 bits for READ/WRITE MODE for SB_RAM map 2019-02-28 16:23:40 -08:00
cells_map.v _ABC macro will map and unmap to this new box 2019-07-12 00:51:37 -07:00
cells_sim.v Add new box to cells_sim.v 2019-07-12 00:52:19 -07:00
ice40_braminit.cc Fix typo in ice40_braminit help msg 2019-03-09 13:24:55 -08:00
ice40_ffinit.cc
ice40_ffssr.cc ice40: Honor the "dont_touch" attribute in FFSSR pass 2018-12-08 22:46:28 +01:00
ice40_opt.cc ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT 2019-07-13 01:11:00 -07:00
ice40_unlut.cc Fixed small typo in ice40_unlut help summary 2019-06-19 16:39:46 -04:00
latches_map.v
Makefile.inc Also update Makefile.inc 2019-04-18 09:58:34 -07:00
synth_ice40.cc Map to and from this box if -abc9 2019-07-12 00:53:01 -07:00